Discrete PIN photodiodes having a slightly doped i-zone with a thickness of several tens of micrometers formed in silicon technology represent prior art. With PIN photodiodes monolithically integrated into silicon chips, however, the problem to be solved is that the dopant concentration of the substrate ranges from 1015 cm−3 and even higher for CMOS wells and n-collectors/epitaxial layers of npn transistors formed in bipolar and biCMOS technology. For this reason, in non-modified SBC (standard buried collector) technology, processes based on bipolar and biCMOS technology, merely PIN photodiodes are feasible which have a thin i-zone (approximately 1 μm in sophisticated processes), thereby resulting in a low efficiency of approximately 26% at 650/670 nm and even less at longer wavelengths (approximately 10% efficiency at 850 nm), as is, for example disclosed by Lim et al., Digest Technical Papers, ISSCC, 1993, pages 696 to 697 and by Kuchta et al., IBM Journal Res. Develop. 39, pages 63 to 72, 1995.
This problem was solved for PIN diodes integrated into bipolar circuitry on silicon substrates by a sophisticated epitaxial process including an intermediate step which was additionally introduced into the overall process, so as to form a 15 μm thick slightly doped i-zone, cf. Yamamoto et al, IEEE Trans. Electron. Dev. 42(1), pages 58-63, 1995. For this purpose, at least three additional masking steps are necessary, thereby significantly contributing to production costs of the process. Another approach in this respect represent so-called lateral trench PIN photodiodes, cf. Yang et al., IEEE Electron. Dev. Lett., pages 395-397, 2002, this approach, however, requiring additional efforts in the integration scheme.
In the CMOS technology, the PIN photodiode integration is already solved, cf. Zimmermann, IEEE Photonics Technology Letters 11, pages 254-256. Here, the i-zone is realized by a slightly doped n-epitaxial layer deposited on the n+ substrate. To this end an additional masking step is necessary.